Programmable multiplexing/demultiplexing system

Details Programmable multiplexing/demultiplexing system Programmable multiplexing/demultiplexing system

1988-09-28

1990-12-04

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

H04J 304

Patent

active

049759132

ABSTRACT:
A programmable multiplexing/demultiplexing system used in a digital communication network, suitable for an ISDN to be developed. The system including a phase adjusting unit, a bit length varying unit, a start timing control unit, and a processor which variably controls the three units. The phase adjusting unit variably controls the phase of an internal clock in accordance with received data, and the thus-adjusted clock is used by the remaining two units. The bit length varying unit variably controls the bit length of the received data. The start timing control variably controls the start timing of each transmission and reception processing carried out alternately by the processor.

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G. Geiger, "IDSN Chipset and Product Requirements"; WESCON 86/Conference Record, vol. 30, Nov. 18th-20th, 1986, pp. 10/1-10/7; Los Angeles, U.S.

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