Error suppressing circuit and method therefor for a phase locked

Details Error suppressing circuit and method therefor for a phase locked Error suppressing circuit and method therefor for a phase locked

1996-08-01

1998-11-17

Pascal, Robert

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 16, 331 14, 331 25, 327156, 327159, H03L 718

Patent

active

058382020

ABSTRACT:
An error suppressing circuit (301) and method therefor for a phase locked loop (PLL) (300). According to one embodiment of the present invention, a transient condition, for example, a bandwidth switch, in the PLL (300) is detected. The PLL (300) is opened for a period of time (509) responsive to detecting the transient condition. The phase of a reference frequency signal (115) and the phase of a output frequency signal (116 or 117) are synchronized after a lapse of the period of time (509). The PLL (300) is closed responsive to the phase of the reference frequency signal (115) and the phase of the output frequency signal (116 or 117) being synchronized. The present envention advantageously reduces the length of time it takes for the PLL (300) to correct for the phase and frequency error generated by the transient condition, and is capable of operating with various types of PLLs.

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