Pulse or digital communications – Repeaters – Testing
Patent
1997-08-07
1999-07-27
Vu, Huy D.
Pulse or digital communications
Repeaters
Testing
370503, 327 48, 375224, G01R 2302, H03D 300, H03K 906
Patent
active
059302941
ABSTRACT:
A counter circuit and a frame control circuit receive a reference clock signal and one or more external clock signals. The counter circuit in combination with the frame control circuit measures the frequency of the external clock signal using either a high frequency measurement mode or a low frequency measurement mode. In the high frequency mode, the number of clocks in the external clock signal are counted for a known time period determined by a high frequency reference clock signal. In the low frequency mode, reference clocks are counted by the counter circuit for a second time period determined by the external clock signal frequency. The measurement circuit automatically switches between the high and low frequency measurement modes according to a minimum clock count value. If the number of external clocks counted during the frequency measurement mode is less than the minimum clock count value, the measurement circuit switches to the alternate frequency measurement mode.
REFERENCES:
patent: 4112358 (1978-09-01), Ashida
patent: 4215308 (1980-07-01), Kusters
patent: 5719782 (1998-02-01), Mitsuoka
patent: 5748570 (1998-05-01), Komoda
Cisco Technology Inc.
Corrielus Jean B
Vu Huy D.
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