Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Patent
1996-11-12
1998-11-17
Wong, Peter S.
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
361 91, 361 56, G05F 140, H02H 320, H02H 900
Patent
active
058381465
ABSTRACT:
An apparatus and method for providing EOS/ESD protection against an EOS/ESD event across first and second pads of an integrated circuit. In one embodiment, the EOS/ESD protection circuit includes an NMOS device having a drain and source respectively coupled to the first and second pads of the integrated circuit, a capacitor coupled between the drain and gate of the NMOS device and a clamping circuit coupled between the gate and the source of the NMOS device to maintain a voltage at the gate less than or equal to a clamping voltage of the clamping circuit. In embodiments of the present invention, the protection circuit includes an active pull down circuit for reducing the voltage across the gate and source of the NMOS device to zero volts a predetermined period of time after the EOS/ESD event, and the protection circuit further includes a current source for providing bias current to the clamping circuit.
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U.S. application No. 08/583,612, Olney, filed Jan. 5, 1996.
U.S. application No. 08/710,183, English, filed Sep. 12, 1996.
Analog Devices Inc.
Patel Rajnikant B.
Wong Peter S.
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