Matrix interconnection system with different width conductors

Details Matrix interconnection system with different width conductors Matrix interconnection system with different width conductors

1988-11-01

1990-12-04

Moffitt, James W.

Static information storage and retrieval

Interconnection arrangements

365 51, G11C 506

Patent

active

049758748

ABSTRACT:
The described embodiment of the present invention utilizes the regular nature of a large number of arrays by providing a grid scheme in the array to provide a low impedance point to point interconnection. In the described embodiment of the present invention a DRAM includes a number of leads running perpendicular to the sense amplifier layout. For a given signal, each lead is interconnected at a bus lead running parallel to the layout of the sense amplifiers. Thus each lead in the parallel array carries a portion of the current. In addition, in this scheme it can be assured that a substantial number of leads will be near any particular sense amplifier which is drawing on the signal provided on the grid array scheme. Because of the close proximity of the parallel conductors, the bus lines to the sense amplifiers need not be as wide as feeder lines in the prior art. Because the parallel grid leads and the bus leads may be much smaller than the leads in the prior art, they may be more compactly arranged in the array.

REFERENCES:
patent: 4636982 (1987-01-01), Takemae et al.
patent: 4807191 (1989-02-01), Flannagan
IBM Technical Disclosure Bulletin-vol. 25, No. 7A, Dec. 1982; pp. 3316-3317.

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