Method of improving a placement in layout design

Details Method of improving a placement in layout design Method of improving a placement in layout design

1987-05-22

1990-12-04

Lall, Parshotam S.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

049758543

ABSTRACT:
A location method in a layout design improves the efficiency of wiring connections among elements. For each row of cell units, the number of cells in variable length blocks and the number of terminals in each block are identified. After counting the available empty cells, the number of empty cells required by each block is calculated based on the number of cells and terminals in the block. For ech row of cells the empty cells are distributed to the blocks. The blocks are then located accordingly on the base structure.

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patent: 4858143 (1989-08-01), Fournier
22nd ACM/IEEE Design Automation Conference (6/23-26, 1985), 1985 Proceedings, The Institute of Electrical and Electronics Engineers, Table of Contents, and pp. 443-448.
VLSI Design, Apr. 1984, vol. V, pp. 3, 35-36, 38-40 and 42-43, Jerry Werner-Editor in Chief.

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