Instruction decode method and arrangement suitable for a decoder

Details Instruction decode method and arrangement suitable for a decoder Instruction decode method and arrangement suitable for a decoder

1988-06-09

1990-12-04

Fleming, Michael R.

Boots, shoes, and leggings

364900, 3642599, 3642624, 3649428, 3649445, 3649462, G06F 300, G06F 1520, G06F 1300

Patent

active

049758390

ABSTRACT:
An instruction decode method and arrangement suitable for a high-speed microprocessor are disclosed. The instruction decode arrangement comprises a high-speed PLA decoder of small capacity for decoding an instruction word having a small execution cycle, a low-speed PLA decoder of large capacity for decoding an instruction word having a large execution cycle, and a circuit for activating the low-speed PLA decoder to cause it to execute instruction decoding when the high-speed PLA decoder is not permitted for the execution of instruction decoding. Instantaneous current noises generated in the PLA decoders can be mitigated to avoid erroneous operations without degrading averaged decoding performance, thereby permitting the microprocessor to operate at high speeds.

REFERENCES:
patent: 4065808 (1977-12-01), Schomberg et al.
patent: 4160289 (1979-07-01), Bambara et al.
patent: 4234958 (1980-11-01), Pipes et al.
patent: 4422141 (1983-12-01), Shoji
patent: 4713749 (1987-12-01), Magar et al.

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