Microcomputer system with dual DMA mode transmissions

Details Microcomputer system with dual DMA mode transmissions Microcomputer system with dual DMA mode transmissions

1990-02-08

1990-12-04

Fleming, Michael R.

Boots, shoes, and leggings

364900, 3642423, 36424231, 36424232, 3649502, G06F 1332, G06F 1314, G06F 1300

Patent

active

049758322

ABSTRACT:
A microcomputer interfaced with an input/output (I/O) device comprises a central processor unit (CPU), a memory, and a direct memory access (DMA) controller, together with a bus system for interconnecting them. The DMA controller can cause the CPU either to be electrically coupled to the bus system for programmed CPU data transmission between the I/O device and the memory, or to be uncoupled therefrom for DMA data transmission therebetween. The CPU is periodically coupled to, and uncoupled from, the bus system for data transmission in a cycle steal mode, in which DMA transmission and programmed CPU transmission alternate at regular intervals, when the CPU is active. When the CPU is inactive, on the other hand, the CPU is held uncoupled from the bus system for data transmission in a sustained DMA mode. More efficient data transmission is thus possible than if data is transmitted in the cycle steal mode regardless of whether the CPU is active or inactive.

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