Page buffer for a multi-level flash memory with a limited number

Details Page buffer for a multi-level flash memory with a limited number Page buffer for a multi-level flash memory with a limited number

1998-06-23

1999-07-27

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular biasing

36518503, 36518905, G11C 700

Patent

active

059301724

ABSTRACT:
A page buffer for a multi-level flash memory array as at least two less latches than threshold values which may be programmed into a memory cell. To enable use of such a page buffer a program/verify method for each cell programs a cell to the level of a most significant binary bit indicating the programming state for the cell. For example, when three threshold levels vt1, vt2 and vt3 are used, the most significant bit representing the threshold level to be programmed is stored in a page buffer latch (312) and the next most significant bit is stored in a page buffer latch (311). The latch (312) is read first and the cell (300) is programmed to vt2 if latch (312) stores a 0. During the program verify procedure, once the vt2 level is obtained, the latch (312) will toggle to a 1. To reuse the latch (312), the latch (312) is then preset to 0, and a read is performed with the latch (312) enabled if latch (311) stores a 0, enabling latch (312) to transition to a 1 if the memory cell (300) is to be programmed to a level vt3. A read is also performed with latch (311) enabled to enable latch (311) to transition to a 1 if the cell (300) is already programmed to vt2. If the latch (312) now stores a 1, the cell (300) is programmed to the level vt3. If the latch (311) stores a 0, the cell (300) is programmed to the level vt1. By reusing the latch (312) to represent the vt3 level in this manner, the third latch (313) is no longer required for programming.

REFERENCES:
patent: 5684739 (1997-11-01), Takeuchi
patent: 5729490 (1998-03-01), Calligaro et al.

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