Test-vector editing system and method

Details Test-vector editing system and method Test-vector editing system and method

1997-10-09

1999-07-27

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, 364491, G06F 1700, G06F 1750

Patent

active

059301490

ABSTRACT:
It is determined whether a given logic state surely fulfills a predetermined logic-state condition, and also it is also determined whether the given logic state possibly fulfills the predetermined logic-state condition. The determination by the first determining unit is performed by determining whether the given logic state is a certain state and also agrees with a logic state required by the predetermined logic-state condition. The determination by the second determining unit is performed by determining whether the given logic state is an uncertain state and therefore does not completely agree with the logic state required by the predetermined logic-state condition. The predetermined logic-state condition is predetermined so that, when a signal having a logic state required by the predetermined logic-state condition appears at a relevant pin of a given electric circuit, no legal DC current flows through the relevant pin.

REFERENCES:
patent: 5051996 (1991-09-01), Bergeson et al.
patent: 5485471 (1996-01-01), Bershteyn
patent: 5581563 (1996-12-01), Penza et al.
Mao et al. "Quretzt: A Quieert Currant Testing Methodology for Detecting Leakage Faults," IEEE, 1990, pp. 280-283.
Nigh et al "Test Generation for Current Testing," IEEE, 1989, pp. 194-200.
Marcel Jacomet "Fantestic: Towards a Powerful Fault Analysis and Test Pattern Generator for ICs," IEEE, 1989, pp. 633-642.
Ferguson "Testing for Parauetic Faults in Static EMOS Circuits," IEEE, 1990, pp. 436-441.
Tinaztepe et al, "Functional Test Program Generator-Through Interactive Graphics," IEEE, 1988, pp. 551-558.
Swari et al, "CrossCheck--A Practical Solution for ASIC Testability," IEEE, 1989, pp. 903-908.
Sy-Yen Kuo "Locating Logic Design Errors Via Test Generation and Don't-Care Propagation," IEEE, pp. 466-471, Sep. 1992.
Frietzemeier et al "Increased CMOS IC Stuck-at-Fault Coverage with Reduced Iddq Test Sets," IEEE, pp. 427-435, Sep. 1990.
Software For Selecting Patterns For Iddq Test Of CMOS, LSI, Nikkei Electronics, (No. 586), Jul. 19, 1993.
Gheewala, T., Introduction to Current Testing, CrossCheck Technology, Inc., pp. 1-4, (No Date).
Product Brief, CurrenTest.TM. Solution, CrossCheck Technology, Inc., (No Date).
Runyon, S., New Tool Synthesizes Iddq Test Structures, Electronic Engineering Times, Issue 793, Apr. 18, 1994.

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