High density BiCMOS circuits and methods of making same

Details High density BiCMOS circuits and methods of making same High density BiCMOS circuits and methods of making same

1989-06-22

1990-12-04

Wojciechowicz, Edward J.

357 42, 357 48, 357 86, H01L 2702

Patent

active

049757644

ABSTRACT:
The area of a BiCMOS integrated circuit is reduced by fabricating portions of the MOS transistor within the bipolar transistor. A BiCMOS integrated inverter circuit having a 35% reduction in area is disclosed.

REFERENCES:
patent: 4825274 (1989-04-01), Higuchi et al.
patent: 4881119 (1989-11-01), Paxman et al.
patent: 4891533 (1990-01-01), Holloway
"0.8 .mu.m Bi-CMOS Technology with High f.sub.T Ion-Implanted Emitter Bipolar Transistor", H. Iwai et al., Technical Digest of the 1987 International Electronic Devices Meeting, Washington, D.C., Dec. 6-9, 1987, pp. 28-31.
"A 1.0 .mu.m N-Well CMOS/Bipolar Technology for VLSI Circuits", J. Miyamoto et al, Technical Digest of the 1983 International Electronic Devices Meeting, Washington, D.C., Dec. 5-7, 1983, pp. 63-66.

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