1979-01-02
1982-05-04
Wojciechowicz, Edward J.
357 22, 357 23, 357 50, 357 51, H01L 2702
Patent
active
043285104
ABSTRACT:
A semiconductor memory cell of the random access, read/write type includes a single combined storage capacitor and access transistor structure. The process for making the cell is compatible with the standard method of making N-channel silicon gate MOS integrated circuits. A thin epitaxial region is grown over an implanted isolating region and a heavily doped bit line in each cell area. A thin gate oxide over the epitaxial layer separates it from a metal address line. A very small cell size is provided.
REFERENCES:
patent: 4053915 (1977-10-01), Cave
Graham John G.
Texas Instruments Incorporated
Wojciechowicz Edward J.
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