Memory interface circuit and access method

Details Memory interface circuit and access method Memory interface circuit and access method

1996-03-01

1999-07-27

Wu, Xiao

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

345103, 345 99, G09G 336

Patent

active

059298324

ABSTRACT:
The memory interface circuit converts an input data signal into multi-scan data signals used for a multi-scan type liquid crystal display. The memory interface circuit includes: a memory for storing one frame of the input data signal corresponding to the display panel, and a control circuit for controlling write/read operations for the memory so that the input data signal is sequentially written in the memory in a single-scan manner, and that data stored in the memory is read out as first and second multi-scan signals in a multi-scan manner. The control circuit controls timing of read operations so that a read operation for the second multi-scan signal is started a predetermined time after that for the first multi-scan signal is started, the predetermined time being equal to a delay time of a write operation of the input data corresponding to the second portion with respect to that corresponding to the first portion.

REFERENCES:
patent: 4630122 (1986-12-01), Morokawa
patent: 4679043 (1987-07-01), Morokawa
patent: 4929058 (1990-05-01), Numao
patent: 5262881 (1993-11-01), Kuwata et al.
patent: 5376944 (1994-12-01), Mogi et al.
patent: 5420604 (1995-05-01), Scheffer et al.
patent: 5457551 (1995-10-01), Culter et al.
patent: 5459482 (1995-10-01), Orien
patent: 5459495 (1995-10-01), Scheffer et al.
patent: 5475397 (1995-12-01), Saidi
patent: 5485173 (1996-01-01), Scheffer et al.
patent: 5489919 (1996-02-01), Kuwata et al.
patent: 5512916 (1996-04-01), Merchant et al.
patent: 5521727 (1996-05-01), Inaba et al.
patent: 5548302 (1996-08-01), Kuwata et al.
patent: 5596344 (1997-01-01), Kuwata et al.
patent: 5598179 (1997-01-01), Orien et al.
Nehring et al, "Ultimate Limits for Matrix Addressing of RMS-Responding Liquid-Crystal Displays",IEEE Transactions on Electron Devices, vol. ED-26, No. 5, May 1979, pp. 795-802.
Ruckmongathan et al, "S3-4 A New Addressing Technique for Fast Responding STN LCDs", Japan Display, '92, pp. 65-68, 1992.
Scheffer et al, "13.4: Active Addressing Method for High-Contrast Video-Rate STN Displays", SID 92 Digest, pp. 228-231, 1992.
Ruckmongathan, "Addressing Techniques for RMS Responding LCDs --A Review", Japan Display '92, pp. 77-80, 1992.
Kudo et al, "Study on Driving Methods for Fast-Responding STN-LSDs", Technical Report of IEICE, EID94-129, ED94-157, SDM94-186, pp. 13-18, 1995.
Ruckmongathan, "A Generalized Addressing Technique for RMS Responding Matrix LCDS", 1988 International Display Research Conference, pp. 80-85, 1988.
Ruckmongathan et al, "A New Addressing Technique for Fast Responding STN LCDs", Japan Display '92, pp. 65-67, 1992.

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