Method of making high voltage, junction isolation semiconductor

Details Method of making high voltage, junction isolation semiconductor Method of making high voltage, junction isolation semiconductor

1996-07-15

1998-11-17

Niebling, John

Fishing, trapping, and vermin destroying

437 26, 437 76, 148DIG10, 148DIG11, H01L 21265

Patent

active

058375538

ABSTRACT:
A two masking level process for a dual buried region epitaxial architecture forms a first masking layer on a surface of a P type substrate. The first masking layer exposes first and second surface portions of the substrate for N+ and P+ buried regions. N type impurities are introduced into the substrate through the first masking layer, so as to form N+ doped regions. A second masking layer is then selectively formed on the first masking layer, such that the second masking layer masks the first aperture, but exposes a second portion of the first masking layer that both includes and surrounds the second aperture. Boron impurities are then introduced through the exposed second aperture of the first masking layer, to a P+ doping concentration. That portion of the first masking layer surrounding the second aperture is removed, and boron impurities are then introduced into exposed second and third surface portions of the substrate, thereby forming a third buried region of the second conductivity type that is adjacent to the second doped region. The composite mask is removed from the substrate, and an N type layer is grown. Due to differences in diffusion coefficients, the P dopant (boron) in the second and third buried regions outruns the N dopant in the second buried region, resulting in the formation of an N+ buried region that is encapsulated in a P+ buried region. The P+ buried region is, in turn, laterally surrounded by a P-type buried region, so as to provide the desired compensation of N ions that are autodoped from the first N+ buried region in the epitaxial layer.

REFERENCES:
patent: 4249970 (1981-02-01), Briska et al.
patent: 4811071 (1989-03-01), Roloff
patent: 5406112 (1995-04-01), Sakane
patent: 5567978 (1996-10-01), Pearce

Affiliated with

Also associated with

Rating

Method of making high voltage, junction isolation semiconductor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making high voltage, junction isolation semiconductor , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making high voltage, junction isolation semiconductor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-883740