Signature compression circuit

Details Signature compression circuit Signature compression circuit

1991-11-26

1993-02-02

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324 731, 371 222, 371 224, G01R 3100, G01R 3128

Patent

active

051840677

ABSTRACT:
A signature compression circuit is employed to test a logic circuit. The signature compression circuit comprises a linear feedback shift register (LFSR) that receives test data from the logic circuit, compresses the data and generates a signature (resultant data) of the test. Output terminals of the logic circuit are grounded via MOS transistors, respectively. When the MOS transistors are OFF, the test data are received by and compressed in the signature compression circuit to form a signature (resultant data) of the test, and the signature in the signature compression circuit is shifted when the MOS transistors are ON.

REFERENCES:
patent: 4517672 (1985-05-01), Pfleiderer et al.
patent: 4661930 (1987-04-01), Tran
patent: 4768196 (1988-08-01), Jou et al.
patent: 4789821 (1988-12-01), Baschiera et al.
"Implementation of Diagnostics and Redundancy on a Programmable Logic Array", IBM Tech. Disc. Bull., vol. 28, #6, Nov. 1985, pp. 2371-2373.
Charles E. Stroud et al., Proceedings of the National Communications Forum, 40 (1986) Part II, Oak Brook, Illinois, USA, pp. 1176-1179.
Konemann et al., "Built-In Logic Block Observation Techniques," IEEE Test Conference, Cherry Hill, N.J., 1979, pp. 37-41.

Affiliated with

Also associated with

Rating

Signature compression circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Signature compression circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signature compression circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-8835