Constant gain phase lock-loop

Details Constant gain phase lock-loop Constant gain phase lock-loop

1992-04-29

1994-05-17

Chin, Stephen

Pulse or digital communications

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375119, 375120, H04L 700, H04L 2536, H04L 2540, H03D 324

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active

053134990

ABSTRACT:
A Phase Lock Loop (PLL) receives input signals from a local area network (LAN) and recovers data and clock signals therefrom. The PLL includes a charge pump which is responsive to pump-up or pump-down signals provided by a phase detector. A level determination circuitry scales the charge pump current in proportion to the time elapsing between transitions in the input signals. The charge pump, phase detector and level determination circuitry provide a constant average amps per radian gain and is insensitive to variations in the input signals.

REFERENCES:
patent: 4167711 (1979-09-01), Smoot
patent: 4745372 (1988-05-01), Miwa
patent: 4803705 (1989-02-01), Gillingham et al.
patent: 5126692 (1992-06-01), Shearer et al.
patent: 5173664 (1992-12-01), Petersen et al.
Patent Abstracts of Japan, 62-67989, Mar. 27, 1987.

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