Method of making a self-aligned field-effect transistor by the u

Details Method of making a self-aligned field-effect transistor by the u Method of making a self-aligned field-effect transistor by the u

1990-05-11

1990-12-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 29, 437 41, 437203, 437912, 437984, 148DIG53, 148DIG111, H01L 2128

Patent

active

049753827

ABSTRACT:
A T-shaped gate of an FET is formed by utilizing the image reverse photolithography process, which includes coating of a semiconductor substrate with a positive resist, initial exposure of an resist outside region, reversal baking, flood exposure of the entire resist layer, and development of the resist layer. The image reverse photolithography process is performed after a dummy gate is formed on the semiconductor substrate. By properly adjusting a light quantity of the flood exposure, a resist pattern can be obtained which has a center hole whose boundary surface is inclined inwardly, and whose bottom surface defines a bottom resist layer thinner than the dummy gate. After removing the dummy gate, a gate material is deposited and then the resist pattern is removed to leave the T-shaped gate.

REFERENCES:
patent: 4551905 (1985-11-01), Chao et al.
patent: 4808545 (1989-02-01), Balasubramanyam et al.
Michael Bolsen, "AZ 5200 Resists for Positive- and Negative Patterning".
K. Yamasaki et al., "Self-Align Implantation for n+-Layer Technology (Saint) for High-Speed GaAs ICs", Electronics Letters, Feb. 4, 1982, vol. 18, No. 3, pp. 119-121.
T. Enoki et al., "Advanced GaAs Saint FET Fabrication Technology and Its Application to Above 9 GHz Frequency Divider", Extended Abstracts of the 17th Conference on Solid State Devices and Materials, Tokyo, 1985, pp. 413-416.
P.C. Chao et al., "Electron-Beam Fabrication of GaAs Low-Noise MESFET's Using a New Trilayer Resist Technique", IEEE Transactions on Electron Devices, vol. ED-32, No. 6, Jun. 1985, pp. 1042-1046.
A. Yasuoka et al., "Registration Accuracy in Focused-Ion-Beam Lithography for the Fabrication of a GaAs FET with a Mushroom Gate", J. Electrochem. Soc., vol. 136, No. 10, Oct. 1989, pp. 3030-3033.
T. Tambo et al., "Low-Noise GaAs MESFET by Dummy-Gate Self-Alignment Technology for MMIC", IEEE GaAs IC Symposium, 1987, pp. 49-52.

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