Fishing – trapping – and vermin destroying
Patent
1990-03-12
1990-12-04
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 33, 437162, 437909, 148DIG11, 148DIG124, 357 34, 357 59, H01L 21265
Patent
active
049753819
ABSTRACT:
This invention discloses a method of manufacturing an SST bipolar transistor, and the manufacturing method is capable of defining the size of a base region of the SST bipolar transistor. An insulating film and a spacer film serving as a spacer are sequentially formed in a bipolar transistor forming region on the main surface of a semiconductor substrate. Thereafter, the spacer film is patterned into a spacer film pattern for defining the size of the base region. A second insulating film, a base electrode pattern and a third insulating film are sequentially formed on the spacer film pattern. A first opening which reaches the spacer film pattern through the second insulating film, the base electrode pattern and the third insulating film is formed. The spacer film pattern is etched from the first opening to form a second opening having a diameter larger than that of the first opening. The insulating film exposed in the second opening is etched. The size of the base region on the major surface of the semiconductor substrate is defined by the size of the second opening.
REFERENCES:
patent: 4675983 (1987-06-01), Uehara
patent: 4818713 (1989-04-01), Feygenson
patent: 4824794 (1989-04-01), Tabata et al.
patent: 4892837 (1990-01-01), Kudo
Ohshima Jiro
Taka Shin-ichi
Hearn Brian E.
Kabushiki Kaisha Toshiba
Nguyen Tuan
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