Static memory cell with dynamic scan test latch

Details Static memory cell with dynamic scan test latch Static memory cell with dynamic scan test latch

1983-10-06

1985-11-19

Atkinson, Charles E.

Excavating

324 73R, G01R 3128, G06F 1100

Patent

active

045546649

ABSTRACT:
A level sensitive scan design (LSSD) Latch Cell that is adaptable to very large scale integrated (VLSI) Semiconductor circuit fabrication is disclosed. The Latch Cell includes a static functional latch and a dynamic test latch, both of which are controlled by a data selector that selects input data from either a functional data source or test data from another test latch in a scan data path.

REFERENCES:
patent: 4071902 (1978-01-01), Eichelberger et al.
patent: 4074851 (1978-02-01), Eichelberger et al.
patent: 4298980 (1981-11-01), Hajdu et al.
patent: 4467431 (1984-10-01), Blum
patent: 4477738 (1984-10-01), Kouba
patent: 4499579 (1985-02-01), Still et al.
McAnney, Method for Sampling Test Points in Logic Circuits, Feb. 1983, IBM Technical Disclosure Bulletin, vol. 25, No. 9, p. 4519.

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