Apparatus and method for calculating B.sup.c (mod n)

Details Apparatus and method for calculating B.sup.c (mod n) Apparatus and method for calculating B.sup.c (mod n)

1997-09-12

1999-07-27

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708606, G06F 772

Patent

active

059283157

ABSTRACT:
Apparatus method for calculating the remainder of B.sup.C modulo n at high speed with minimum hardware resources, while securing the safety of the key in a cryptographic system. The apparatus comprises circuitry including registers for executing an initial and normal cycles, cumulating and storing the calculation result of each cycle and for outputting from a least significant bit. The initial cycle of the calculation includes a step of calculating a remainder of an m-bit input modulo n and a step of holding the result of the calculation. The normal cycle of the calculation includes a step of doubling the result of the calculation, and calculating a remainder of the doubled result of the calculation modulo n and a step of holding the next result of the calculation and for repeatedly executing the normal cycle m-2 times after the first normal cycle. The calculation result of each previous normal cycle is used in each successive normal cycle.

REFERENCES:
patent: 4532638 (1985-07-01), Lagger et al.
patent: 5289397 (1994-02-01), Clark et al.
patent: 5479365 (1995-12-01), Ogura
patent: 5513133 (1996-04-01), Cressel et al.
patent: 5793660 (1998-08-01), Rentschler

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