Parallel adder circuit with sign bit decoder for multiplier

Details Parallel adder circuit with sign bit decoder for multiplier Parallel adder circuit with sign bit decoder for multiplier

1988-03-21

1989-11-07

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 752

Patent

active

048796778

ABSTRACT:
A parallel adder circuit includes a partial product adding circuit for adding one-bit partial products together in order total to a plurality of partial products, and sign bit decoder circuit for decoding sign bits of a given bit number to provide a total sum of the sign bits, and supply this total sum to the partial product adding circuit at given bits. In a multiplier utilizing Booth's algorithm, a decoder circuit is used for decoding sign bits of the partial product to provide the total sum of all the sign bits, and a decoded output is supplied to the partial product adding circuit. Therefore, the number of higher bit inputs can be reduced and the number of full adders in the partial product adding circuit can be decreased.

REFERENCES:
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4748582 (1988-05-01), New et al.
patent: 4748584 (1988-05-01), Noda
Waser et al., "Real Time Processing Gains Ground with Fast Digital Multiplier", Electronics, Sep. 29, 1977, pp. 93-99.

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