Electronic phase detector having an output which is proportional

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307511, 307514, 307516, 307519, 307529, 328 55, 331 25, 375120, H03L 710

Patent

active

045203199

ABSTRACT:
A phase detecting circuit for use in a phase-locked loop is provided with a pair of bistable circuits such as type D flip-flops. One of the circuits is clocked by a controlled output signal from a voltage controlled oscillator, and reset by an input reference signal. The other of the bistable circuits is clocked by an inverted input reference signal and reset by an inverted output signal from the voltage controlled oscillator. The Q and NOT Q outputs of these bistable circuits are fed to a voltage divider and shifted in magnitude by a fixed amount such that the phase error detection signal is a constant zero when the input reference signal and output signals are in phase.

REFERENCES:
patent: 3986125 (1976-10-01), Eibner
patent: 4020422 (1977-04-01), Underhill
patent: 4055814 (1977-10-01), Abraham et al.
patent: 4129748 (1978-12-01), Saylor
patent: 4246545 (1981-01-01), Reisfeld
patent: 4316150 (1982-02-01), Crosby
patent: 4321483 (1982-03-01), Dugan
patent: 4445094 (1984-04-01), Ryan
Markus, "Square to Sine with PLL", Modern Electronic Circuits Reference Manual McGraw-Hill Book Co., New York, 1980, p. 424.

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