High voltage drifted-drain MOS transistor

Details High voltage drifted-drain MOS transistor High voltage drifted-drain MOS transistor

1988-05-16

1988-12-27

Edlow, Martin H.

357 43, 357 35, H01L 2978, H01L 2702, H01L 2972

Patent

active

047944366

ABSTRACT:
A heavily doped P region is formed at the end of a lightly doped P- drain extension adjacent to the channel of a P channel MOS transistor. If the PMOS transistor is fabricated in an N-well surrounded by P- type material, a parasitic vertical transistor is formed which may be undesireably biased into its active mode if the voltage at the P+ drain of the PMOS transistor causes the P+ drain and N- body to be forward biased. When this vertical transistor conducts, power is wasted. The addition of the P region formed at the end of the lightly doped drain greatly increases the current gain of the parasitic lateral transistor, which is biased into its active mode under the same conditions which bias the vertical transistor into its active mode. The current through the lateral parasitic transistor, which may be recaptured, is thus much greater than the current through the vertical parasitic transistor, resulting in less power loss when the parasitic transistors are biased into their active modes under abnormal conditions.

REFERENCES:
patent: 4669177 (1987-06-01), D'Arrigo et al.

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