1987-07-06
1988-12-27
Edlow, Martin H.
357 55, 357 43, H01L 2978, H01L 2906, H01L 2702
Patent
active
047944340
ABSTRACT:
A DRAM memory cell has a trench capacitor and a transistor. The trench of the trench capacitor penetrates to a buried layer which acts as the primary portion of one of the plates of the capacitor. When the buried layer is the same conductivity type as the transistor of the memory cell, the buried layer is biased to a voltage selected to reduce the maximum voltage across the capacitor. This allows for a reduction in the thickness of the dielectric which coats the trench which increases the capacitance of the capacitor. When the buried layer is of the opposite conductivity type from the transistor type of the memory cell, there is no parasitic MOS transistor formed between the primary portion of the capacitor plate and the source of the transistor of the memory cell.
REFERENCES:
patent: 4707456 (1987-11-01), Thomas et al.
Clingan Jr. James L.
Edlow Martin H.
Fisher John A.
Limanek Robert P.
Motorola Inc.
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