Non-volatile semiconductor memory with non-uniform gate insulato

Details Non-volatile semiconductor memory with non-uniform gate insulato Non-volatile semiconductor memory with non-uniform gate insulato

1986-02-19

1988-12-27

James, Andrew J.

357 45, 357 2314, 357 239, 357 2312, H01L 2978

Patent

active

047944331

ABSTRACT:
A non-volatile semiconductor memory device has source and drain regions disposed in spaced apart relation adjacent the surface of a semiconductor substrate to define in the substrate a channel region having a first channel region portion in contract with the drain region and a second channel region portion between the first channel region portion and the source region. A floating gate electrode is disposed over the channel region between the source and drain regions, and a gate insulating layer is disposed between the channel region and the floating gate electrode. A writing drain voltage of one polarity is applied to the drain region and a writing floating gate voltage of the same polarity is applied by capacitance coupling to the floating gate electrode in order to more strongly invert the first channel region portion and more weakly invert the second channel region portion relative to one another to effect the injection of electric charges which comprise part of the channel current into the floating gate electrode from a position where the first channel region portion under strong inversion is in contact with the second channel region portion under weak inversion, the position being more distant from the drain region than the width of a depletion layer under the drain region formed between the drain region and the semiconductor substrate.

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