Excavating
Patent
1996-06-06
1998-10-06
Tu, Trinh L.
Excavating
371 572, 377 39, 395557, G06F 1100, H03K 2100
Patent
active
058188479
ABSTRACT:
A programmable clock circuit generates a real time clock value, which is incremented in response to a real time clock increment signal. The real time clock increment signal is generated after a selected number of ticks of a system clock signal, with the number of ticks being determined by whether it is operating in a normal mode or an error compensation mode. In the normal mode, the real time clock increment signal is generated after a selected number of ticks of the system clock signal, which results in an increasing cumulative timing error. In the error compensation mode, the real time clock increment signal will be generated after a number of ticks of the system clock signal selected so as to reduce this cumulative error. The programmable clock circuit keeps track of the cumulative error in the real time clock signal while operating in the normal mode. When the cumulative error reaches a selected maximum error, the circuit changes to the error compensation mode to enable a reduction in the cumulative error in the real time clock signal.
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patent: 3866024 (1975-02-01), Williams
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patent: 4989223 (1991-01-01), Katayose et al.
patent: 5495451 (1996-02-01), Cho
patent: 5657361 (1997-08-01), Inagaki et al.
Jordan Richard A.
Sun Microsystems Inc.
Tu Trinh L.
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