Semiconductor memory drive capable of canceling power supply noi

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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365 51, 365 63, G11C 800

Patent

active

060026367

ABSTRACT:
This invention discloses the layout of word line driving circuits for driving word lines. A semiconductor memory device includes a memory cell array having a bit line, n memory cells connected to the bit line, and n word lines respectively connected to the n memory cells. The semiconductor memory device further includes n/2 first word line driving circuits for driving n/2 word lines of the n word lines, and n/2 second word line driving circuits for driving the remaining n/2 word lines of the n word lines. The second word line driving circuits are arranged at the positions where the second word line driving circuits face the first word line driving circuits via the memory cell array.

REFERENCES:
patent: 4044340 (1997-08-01), Itoh
patent: 5363326 (1994-11-01), Nakajima
patent: 5383160 (1995-01-01), Furuyama
patent: 5511027 (1996-04-01), Shimizu
patent: 5740107 (1998-04-01), Lee

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