Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1997-12-02
1999-12-14
Nelms, David
Static information storage and retrieval
Addressing
Plural blocks or banks
36523004, 36523001, G11C 800
Patent
active
060026316
ABSTRACT:
Even-numbered columns are arranged in the first memory cell array (bank), and odd-numbered columns are arranged in the second memory cell array (bank). A column address signal is input to an adder through a buffer. When data is read out of two or more columns, the adder generates a column address signal whose address value is more than that of the column address signal by one. The adder supplies a first column decoder with a column address signal for addressing an even-numbered column and supplies a second column decoder with a column address signal for addressing an odd-numbered column. Since the even-numbered columns and odd-numbered columns are arranged in their separate memory cell arrays, data read out of continuous two or more columns do not collide with each other.
REFERENCES:
patent: 3846765 (1974-11-01), De Vries
patent: 4247920 (1981-01-01), Springer et al.
patent: 5247644 (1993-09-01), Johnson et al.
patent: 5261064 (1993-11-01), Wyland
patent: 5453957 (1995-09-01), Norris et al.
patent: 5590084 (1996-12-01), Miyano et al.
patent: 5748555 (1998-05-01), Park
Haga Ryo
Miyano Shinji
Yabe Tomoaki
Kabushiki Kaisha Toshiba
Nelms David
Nguyen Tuan T.
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