Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1982-12-01

1986-07-22

Popek, Joseph A.

Static information storage and retrieval

Addressing

365189, G11C 800

Patent

active

046023569

ABSTRACT:
A semiconductor memory device operates under a so-called address multiplex access method. A row part of the device is enabled by receiving a row address strobe (RAS) signal. A column part of the device is enabled by simultaneously receiving both a column address strobe (CAS) signal and a timing control signal supplied from the row part during its enable state. A column address buffer in the column part is enabled by simultaneously receiving both the CAS signal and a timing control signal. The timing control signal is produced from a circuit when it detects and holds the RAS signal.

REFERENCES:
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4376989 (1983-03-01), Takemae
patent: 4397001 (1983-08-01), Takemae
Patent Abstracts of Japan, vol. 3, No. 28, (E-96), Mar. 9, 1979, p. 31 E 96 & JP-A-54 6429, (Tokyo Shibaura Denki K.K.) 01-18-1979.
Patent Abstracts of Japan, vol. 3, No. 36, (E-100), Mar. 27, 1979, p. 62 E 100 & JP-A-54 14131 (Fujitsu K.K.) 02-02-1979.
IEEE International Solid-State Circuits Conference, Feb. 15, 1980, pp. 230-231, IEEE, New York, L. S. White et al., "Session XVII: Random Access Memories", p. 230, left-hand col., line 44-right-hand col., line 11, Figs. 3, 4.
European Search Report of 06-28-83 by Examiner Degraeve at The Hague.

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