Patent
1995-12-19
1999-01-05
Lall, Parshotam S.
395378, 395569, 39580023, 395678, G06F 900
Patent
active
058570969
ABSTRACT:
An apparatus (e.g. a microarchitecture of a microprocessor) comprising a plurality of tags associated with a first storage area indicating that locations in the first storage area are either empty or non-empty responsive to execution of floating point instructions which modify data contained in the first storage area. A first circuit is coupled to the plurality of tags which sets only the plurality of tags to an empty state responsive to receipt of a first instruction. The first instruction indicates termination of execution of instructions which operate upon the packed data stored in the first storage area. The apparatus further comprises a second circuit coupled to the plurality of tags for setting the plurality of tags to a non-empty state responsive to receipt of a second instruction (or instructions). The second instruction specifies an operation upon packed data stored in the first storage area. The second circuit further sets the plurality of tags to indicate execution of instructions which operate upon the packed data. This apparatus advantageously provides a architecture (e.g. a microarchitecture for a microprocessor) for clearing the packed data state at the end of executed blocks of packed data instructions to leave the floating point state in a clear condition for subsequent operations (e.g. blocks of executed floating point instructions).
REFERENCES:
patent: 3711692 (1973-01-01), Batcher
patent: 3723715 (1973-03-01), Chen et al.
patent: 4161784 (1979-07-01), Cushing et al.
patent: 4229801 (1980-10-01), Whipple
patent: 4393468 (1983-07-01), New
patent: 4418383 (1983-11-01), Doyle et al.
patent: 4498177 (1985-02-01), Larson
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4771379 (1988-09-01), Ando et al.
patent: 4989168 (1991-01-01), Kuroda et al.
patent: 4992938 (1991-02-01), Cocke et al.
patent: 5008812 (1991-04-01), Bhandarkar et al.
patent: 5095457 (1992-03-01), Jeong
patent: 5127098 (1992-06-01), Rosenthal et al.
patent: 5187679 (1993-02-01), Vassiliadis
patent: 5241635 (1993-08-01), Papadopoulos et al.
patent: 5267350 (1993-11-01), Matsubara et al.
patent: 5367650 (1994-11-01), Sharangpani et al.
patent: 5467473 (1995-11-01), Kahle et al.
patent: 5481719 (1996-01-01), Ackerman et al.
patent: 5493687 (1996-02-01), Garg et al.
patent: 5499352 (1996-03-01), Clift et al.
patent: 5507000 (1996-04-01), Stewart et al.
patent: 5519841 (1996-05-01), Sager et al.
patent: 5522051 (1996-05-01), Sharangpani
patent: 5535397 (1996-07-01), Durante et al.
patent: 5537606 (1996-07-01), Byrne
patent: 5546554 (1996-08-01), Yung et al.
patent: 5560035 (1996-09-01), Garg et al.
patent: 5634118 (1997-05-01), Blomgren
patent: 5649225 (1997-07-01), White et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5687336 (1997-11-01), Shen et al.
patent: 5696955 (1997-12-01), Goddard et al.
patent: 5701508 (1997-12-01), Glew et al.
i860TM Microprocessor Family Programmer's Refernce Manual, Intel Corporation (1992), Ch. 2, 9, 10, 11.
International Search Report for PCT/US96/20572 mailed Mar. 21, 1997, 1 page.
International Search Report for PCT/US96/20522 mailed Apr. 23, 1997, 3 pages.
International Search Report for PCT/US96/20516 mailed Apr. 18, 1997, 1 page.
Margulis, Neal Chapter 9: Operating System Support, i860 Microprocesor Architecture, (1990), p. 245.
Pentium TM Processor User's Manual Vol. 3: Architecture and Programming Manual, Intel Corporation (1993), Ch. 25, pp. 81, 85, 90, 94-96, 102-103, 106, 115, 117, 127, 137.
J. Shipnes, Graphics Processing with the 88110 RISC Microprocessor, IEEE (1992), pp. 169-174.
MC88110 Second Generation RISC Microprocessor User's Manual, Motorola Inc. (1991).
Errata to MC88110 Second Generation RISC Microprocessor User's Manual, Motorola Inc. (1992), pp. 1-11.
MC88110 Programmer's Reference Guide, Motorola Inc. (1992), pp. 1-4.
i860.TM. Microprocessor Family Programmer's Reference Manual, Intel Corporation (1992), Ch. 1, 3, 8, 12.
R. B. Lee, Accelerating Multimedia With Enhanced Microprocessors, IEEE Micro (Apr. 1995), pp. 22-32.
TMS320C2x User's Guide, Texas Instruments (1993) pp. 3-2 through 3-11; 3-28 through 3-34; 4-1 through 4-22; 4-41; 4-103; 4-119 through 4-120; 4-122; 4-122; 4-150 through 4-151.
L. Gwennap, New PA-RISC Processor Decodes MPEG Video, Microprocessor Report (Jan. 1994), pp. 16,17.
SPARC Technology Business, UltraSPARC Multimedia Capabilities On-Chip Support for Real-Time Video and Advanced Graphics, Sun Microsystems (Sep. 1994).
Y. Kawakami et al., LSI Applications: A Single-Chip Digital Signal Processor for Voiceband Applications, Solid State Circuits Conference, Digest of Technical Papers; IEEE International (1980).
B. Case, Philips Hopes to Displace DSPs with VLIW, Microprocessor Report (Dec. 94), pp. 12-18.
N. Margulis, i860 Microprocessor Architecture, McGraw Hill, Inc. (1990) Ch. 6, 7, 8, 10, 11.
Pentium Processor User's Manual Vol. 3: Architecture and Programming Manual, Intel Corporation (1993), Ch. 1, 3, 4, 6, 8, and 18.
Bistry David
Dulong Carole
Eitan Benny
Kowashi Eiichi
Mennemeier Larry
Intel Corporation
Lall Parshotam S.
Patel Gautam R.
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