Patent
1996-10-02
1999-01-05
Harvey, Jack B.
G06F 1300
Patent
active
058570845
ABSTRACT:
A system and method for reducing the time required to access peripheral devices or to perform peripheral device operations in a multiple bus architecture or hierarchical bus structure environment. A memory device is used to remember which addresses generated responses on which busses. The memory device is accessed in subsequent operations to eliminate the procedure for determining which bus is attached to the desired peripheral.
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Harvey Jack B.
Myers Paul R.
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