Patent
1996-08-30
1999-01-05
An, Meng-Ai T.
395306, 395308, 395290, 395293, G06F 1300
Patent
active
058570810
ABSTRACT:
While a PCI master on an external bus is executing a transaction on an internal PCI bus, if a bus access request signal (REQ#) output from a PCI device on the internal PCI bus, priority of which is higher than that of the PCI master, is asserted, a PCI bus arbiter deasserts a bus access enable signal (GNT#) corresponding to the PCI master. A request and grant manager informs the PCI master of GNT# by using a serial GNT# through an external PCI bus bridge connected to the internal PCI bus and the external PCI bus. Before the transaction executed by the PCI master ends, when the external PCI bus bridge recognizes that a device on the external PCI bus is a target specified by a transaction of the PCI device as a new bus master, it informs the PCI device of a target retry.
REFERENCES:
patent: 5559968 (1996-09-01), Stancil et al.
patent: 5632021 (1997-05-01), Jennings et al.
Intel Article, "Peripheral Components," pp. 3-33 through 3-50, (1993).
"Mobile PC/PCI DMA Arbitration and Protocols," Intel Corporation, Apr. 1996, Revision 2.2, pp. 1-27.
PCI Local Bus Specification, PCI Special Interest Group, Revision 2.1 (1995).
PCI Local Bus Specification, PCI Special Interest Group, Revision 2.0 (1995).
An Meng-Ai T.
Dharia Rupal D.
Kabushiki Kaisha Toshiba
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