Single wafer moated process

Details Single wafer moated process Single wafer moated process

1987-11-18

1988-12-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 48, 437 67, 437225, 437 3, 148DIG135, 148DIG164, 357 30, H01L 2176

Patent

active

047940921

ABSTRACT:
The present invention is directed to the construction of an integrated circuit chip, and to the method of making such a chip from a plate or wafer. In accordance with the present invention a chip is formed to have conductive edge portions disposed on an insulator surface, which portions optionally may further be expanded into a pad. The insulating material electrically isolates the conductive edge portions from the semiconductive body of the chip. The invention may be implemented in redundant fashion to effect a multiplicity of electrical connections to a set of bulk semiconductor integrated circuits formed on the wafer.
Each exposed conductive portion on a chip edge and its optional surrounding conductive pad may be reliably surrounded by insulator so that electrical shorts to non-insulating regions are not experienced. By this edge surface structure integrated circuit elements may be stacked in an array, and electrically connected at the edge surfaces thereof, without hazard that any electrical regions of the integrated circuit elements may be contacted, save intentionally through a conductive lead or film connected to the pads.

REFERENCES:
patent: 3352730 (1967-11-01), Murch, Jr.
patent: 4040169 (1977-08-01), Rose
patent: 4403238 (1983-09-01), Clark
patent: 4468857 (1984-09-01), Christian et al.
patent: 4551629 (1985-11-01), Carson et al.
patent: 4618763 (1986-10-01), Schmitz
patent: 4624047 (1986-11-01), Tani

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