Multiplexed-access scan testable integrated circuit

Details Multiplexed-access scan testable integrated circuit Multiplexed-access scan testable integrated circuit

1984-12-28

1986-07-22

Karlsen, Ernest F.

Electricity: measuring and testing

Plural, automatically sequential tests

371 15, G01R 3128

Patent

active

046022104

ABSTRACT:
A testable integrated circuit contains additional circuitry which defines--when operable in a test mode--a plurality of scan paths in each of which are connected in series a plurality of bistable elements (specifically, special scan path flip-flops) isolated from the integrated circuit combinational circuits. The input and output ends of these scan paths are connected by multi-level demultiplexer and multiplexer arrangements with the input and output pins, respectively, of the integrated circuit. The last level demultiplexer and the last level multiplexer include first groups of connections with the input and output ends of the scan paths, respectively, and second groups of connections with the input and output ends of the mission logic. The demultiplexers, the multiplexers and the scan path flip-flops are operable between mission and test modes upon the application of a mode control signal thereto. When the circuit is in the test mode, a test signal applied to the inputs of the scan paths is monitored at the output ends of the paths to indicate the correctness of operation of the SPFF's in each path. Composite test vectors are then applied for testing the combinational circuits via the SPFF's and primary inputs to the said combinational circuits.

REFERENCES:
patent: 4267463 (1981-05-01), Mayumi
patent: 4286173 (1981-08-01), Oka et al.
Schraeder, M. W.; "Multiplexed Measuring . . . "; EDN; May 12, 1982; pp. 187-190.
Faran, Jr., J. J.; "Methods of Assignment . . . "; 1982, IEEE Test Conference; May 1982; pp. 641-647.

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