Data processing system with a pipelined structure for editing tr

Details Data processing system with a pipelined structure for editing tr Data processing system with a pipelined structure for editing tr

1987-04-20

1989-11-07

Williams, Jr., Archie E.

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3642318, 364274, 3642741, 3642751, 3642755, 3642765, 3642769, 364285, 3642853, 3642854, 371 165, 371 19, G06F 938, G06F 1122, G06F 1126, G06F 1128

Patent

active

048796468

ABSTRACT:
A microprocessor having a multi-stage pipeline structure, comprises: a status flip-flop having its output changing when the instruction code of a predetermined instruction is decoded in the microprocessor; a circuit for outputting the output of the status flip-flop in synchronism with the output timing of an address for the bus cycle period of the microprocessor; and a circuit for sequentially storing the information, which appears at the input/output terminals of the microprocessor, as time-series data outside of the microprocessor. The time-series data is edited by discriminating the bus cycle of the microprocessor belongs to the bus cycle following an instruction on or before the predetermined instruction for changing the output of the status flip-flop or the bus cycle following an instruction on or after the predetermined instruction, with reference to the information outputted from the status flip-flop inside of the microprocessor to the outside of the same.

REFERENCES:
patent: 4390946 (1983-06-01), Lane
patent: 4430706 (1984-02-01), Sand
patent: 4477872 (1984-10-01), Losq et al.
"Error Tracing Arrangement of a Pipeline Processor ," IBM Technical Disclosure Bulletin, vol. 28, No. 2, Jul. 1985, pp. 621-624.

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