Encoder and decoder for an SEC-DED-S4ED rotational code

Details Encoder and decoder for an SEC-DED-S4ED rotational code Encoder and decoder for an SEC-DED-S4ED rotational code

1997-02-18

1999-01-05

Moise, Emmanuel L.

Excavating

371 3703, 371 3708, 371 3711, 371 3712, H03M 1300

Patent

active

058569871

ABSTRACT:
A computer system employs a SEC-DED-S4ED rotational error control code (ECC) wherein all columns of H matrix are linearly independent and have an odd weight, and are arranged to allow detection of 4-bit byte errors. The ECC includes check bits arranged in a specific manner in designated columns of the matrix to permit detection and correction of single bit errors, as well as detection of double, triple and quadruple bit errors. The computer system employing the ECC also includes a data path having a variety of implementations; e.g., a single 72-bit path, two 36-bit paths, or a single 36-bit path.

REFERENCES:
patent: 3825893 (1974-07-01), Bossen et al.
patent: 4509172 (1985-04-01), Chen
patent: 4692922 (1987-09-01), Kiriu et al.
patent: 5040179 (1991-08-01), Chen
Rao, T.R.N. & E. Fujiwara: Error-Control Coding for Computer Systems, 1989, pp. 221-299.

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