Sample-and-hold circuit having reduced parasitic diode effects a

Details Sample-and-hold circuit having reduced parasitic diode effects a Sample-and-hold circuit having reduced parasitic diode effects a

1998-04-06

1999-12-14

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 95, 327 96, H03K 1700, G11C 2702

Patent

active

060022779

ABSTRACT:
An integrated S/H circuit includes a first field-effect transistor (FET) formed on a substrate with a sampling capacitor, and a buffer amplifier having an input connected to the sampling capacitor and an output connectable to the body of the first FET. The buffer amplifier thereby reduces undesired effects from a parasitic diode formed by the body and sampling capacitor. More particularly, the first FET preferably has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time, and for disconnecting the input signal from the sampling capacitor during a holding time. The circuit may include one or more switches for connecting the body of the first FET to the output of the buffer amplifier during the holding time to thereby apply a holding voltage from the sampling capacitor to the body of the first FET. The holding voltage overcomes the voltage droop as would otherwise be caused by the parasitic diode. The switches may also connect the body of the first FET to a supply voltage during the sampling time. In addition, the buffer amplifier may have a substantially unity gain.

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