Semiconductor memory device and memory module using the same

Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...

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365200, G01C 1300

Patent

active

058187928

ABSTRACT:
Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.

REFERENCES:
patent: 4688219 (1987-08-01), Takemae
patent: 4727516 (1988-02-01), Yoshida et al.
patent: 4837747 (1989-06-01), Dosaka et al.
patent: 5193071 (1993-03-01), Umina et al.
patent: 5262993 (1993-11-01), Horiguchi et al.

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