Methods for fabricating multichip semiconductor structures with

Details Methods for fabricating multichip semiconductor structures with Methods for fabricating multichip semiconductor structures with

1997-01-02

1998-09-15

Chin, Christopher L.

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

437 51, 365 51, 257777, 257676, 257203, 257320, 257723, G11C 506

Patent

active

058077910

ABSTRACT:
Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure. Also disclosed is removing, adding or balancing ESD circuit loading on input/output nodes of a multichip stack. Various techniques are presented for selective removal of ESD circuitry from commonly connected I/O nodes. Any circuitry interfacing with an external device may be rebalanced at the multichip level using this concept.

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