MOS Static decoding circuit

Details MOS Static decoding circuit MOS Static decoding circuit

1978-11-27

1981-04-28

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 365230, H03K 19094, H03K 19017, G11C 800

Patent

active

042648289

ABSTRACT:
A metal-oxide-semiconductor (MOS) static decoding circuit for selecting an addressed line in a high density memory array, or the like, is disclosed. The circuit may be laid-out along array lines where the lines have a pitch of approximately 12.25 microns. Three levels of decoding are employed. The highest level permits the pulling-up of a common node in the second level decoder. The third level of decoding selects one of a plurality of array lines coupled to this node. Zero threshold voltage MOS devices are employed for coupling the first and third decoders to the second decoder.

REFERENCES:
patent: 3863230 (1975-01-01), Regitz et al.
patent: 3964030 (1976-06-01), Koo
patent: 4079462 (1978-03-01), Koo
patent: 4095282 (1978-06-01), Oehler
patent: 4096584 (1978-06-01), Owen et al.
patent: 4124900 (1978-11-01), Smith et al.
Radzik, "Multiple Image Read-Only Storage," IBM Tech. Discl. Bull.; vol. 14, No. 12, pp. 3737-3738, 5/72.
Masuhara et al., IEEE Journal of Solid-State Circuits, vol. SC-7, No. 3, pp. 224-231, 6/72.

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