Semiconductor memory device

Static information storage and retrieval – Addressing – Plural blocks or banks

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36523006, 36518905, 36523008, G11C 700

Patent

active

058187871

ABSTRACT:
A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.

REFERENCES:
patent: 5177706 (1993-01-01), Shinohara et al.
patent: 5455798 (1995-10-01), McClure
patent: 5521878 (1996-05-01), Ohtani et al.
patent: 5619456 (1997-04-01), McClure

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