Non-volatile semiconductor memory device with block erase functi

Details Non-volatile semiconductor memory device with block erase functi Non-volatile semiconductor memory device with block erase functi

Filed on

1996-04-12

Date issued

1998-10-06

Examiner

Yoo, Do Hyun

Patent Class

Static information storage and retrieval

SubClass

Floating gate

SubSubClass

Particular connection

Other Related Categories

36518511, 36518529, 365218, 36523003, G11C 1600

Type

Patent

Status

active

Patent number

058187561

Description

ABSTRACT:
At the time of erasing data, common gate lines connected to selective gates are charged with Vcc or a voltage higher than. This enables reliable cut-off of transfer transistors at the time of erasing data. Accordingly, even if the potential of the selective gates increase in accordance with an increase in the substrate potential of a memory cell portion, current leakage through the transistors can be prevented. Further, at the time of erasing data, the common gate lines are set to V.sub.L slightly higher than Vss. This can enhance the cut-off characteristics of transfer transistors in a non-selected block, and prevent erroneous erasion of data stored in memory cells included in the non-selected block.

REFERENCES:
patent: 5357462 (1994-10-01), Tamaka et al.
patent: 5568420 (1996-10-01), Lim et al.
patent: 5568421 (1996-10-01), Aritome
"A Quick Intelligent Page-Programming Architecture and A Shielded Bitline Sensing Method for 3V-Only NAND Flash Memory" in IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994.

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