Data interpolating circuit using a two data word memory

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364723, G06F 1110

Patent

active

046399208

ABSTRACT:
An interpolation circuit and method corrects a data word having an error by either substituting the most recent prior correct data word or substituting the mean value of the most recent prior correct data word and the data word subsequent to the one having the error. The method is carried out using a novel architecture having memory access control. A RAM stores the most recent prior correct word, A.sub.j, which will be the current word A.sub.n if A.sub.n has no error. If the subsequent workd A.sub.n+1 is without error it is stored. The two memory locations are, in effect, reversible, to enable the subsequent work A.sub.n+1 to become the most recent correct prior word, A.sub.j, for subsequent processing, where appropriate, using a minimum of hardware.
The most recent prior word A.sub.j (which may be A.sub.n) is read to an adder which performs addition and division by two. Depending upon the error content of A.sub.n and A.sub.n+1, A.sub.j is either added to itself or to A.sub.n+1 to obtain the final interpolated data. All words are divided into upper-half and lower-half portions to cut down on the hardware required.

REFERENCES:
patent: 4430736 (1984-02-01), Scholz
patent: 4451921 (1984-05-01), Odaka
patent: 4497055 (1985-01-01), Hoshino et al.

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