Method of forming a fiducial for aligning an integrated circuit

Details Method of forming a fiducial for aligning an integrated circuit Method of forming a fiducial for aligning an integrated circuit

1997-11-26

1999-12-14

Niebling, John F.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

438401, 438975, 148DIG102, H01L 2176

Patent

active

060017031

ABSTRACT:
A fiducial for aligning an integrated circuit die. In one embodiment, the fiducial is configured to be exposed by laser chemical etching through a silicon substrate through the back side of a C4 packaged integrated circuit die. The presently described fiducial includes floating diffusion regions disposed in the substrate. An oxide layer free of metal contacts is disposed over the diffusion regions within the fiducial region of the integrated circuit. A metal pattern layer is disposed beneath the oxide layer to provide alignment information. The metal pattern layer is configured to be visible through the oxide layer after the silicon substrate has been removed from the fiducial region. A light block is disposed between the metal pattern layer and an underlying epoxy underfill layer to minimize the risk of an excessive amount of light from being exposed to the underlying epoxy layer, which minimizes the risk of the epoxy layer from damaging the integrated circuit from excessive light exposure. Since the presently described fiducial does not include any contacts in the oxide layer, the additional step of utilizing a focus ion beam mills no longer necessary and the presently described fiducial therefore only needs to be etched with a laser chemical etcher to be exposed.

REFERENCES:
patent: 4479830 (1984-10-01), Koshino et al.
patent: 5241454 (1993-08-01), Ameen et al.
patent: 5304839 (1994-04-01), Chen et al.
patent: 5365103 (1994-11-01), Brown et al.
patent: 5612573 (1997-03-01), Lewis
"Shield for Protecting an Integrated Circuit During Etch of Silicon Substrate," IBM Technical Disclosure Bulletin, vol. 38 (2), 1995.

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