High aspect ratio low resistivity lines/vias by surface diffusio

Details High aspect ratio low resistivity lines/vias by surface diffusio High aspect ratio low resistivity lines/vias by surface diffusio

1996-02-20

1999-01-05

Nguyen, Ngoc-Yen

Stock material or miscellaneous articles

All metal or with adjacent metals

Composite; i.e., plural, adjacent, spatially distinct metal...

428641, 428665, 428614, 428650, 428672, 428673, 257764, H01L 2912

Patent

active

058560262

ABSTRACT:
A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap of W.sub.x Ge.sub.y. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

REFERENCES:
patent: 3167462 (1965-01-01), Winkelman
patent: 3222630 (1965-12-01), Gorman
patent: 3501829 (1970-03-01), Corwin
patent: 4188710 (1980-02-01), Davey et al.
patent: 4207546 (1980-06-01), Grudkowski
patent: 4301188 (1981-11-01), Niehaus
patent: 4321099 (1982-03-01), Stirn et al.
patent: 5121174 (1992-06-01), Forgerson, II et al.
patent: 5262354 (1993-11-01), Cote et al.
patent: 5308794 (1994-05-01), Tu
Merriman, "A Dictionary of Metallurgy", TN609 M47, 1958, p. 5. (no month).
Hansen, "Constitution of Binary Alloys", 2.sup.nd edition, TA 490 H27aE 1958, p. 779 (no month).
Massalski et al, "Binary Alloy Phase Diagrams", vol. 2, TN 690 B5 1986, p. 1260 (no month).
"Binary Alloy Phase Diagrams", Massalski et al, vol. 1, TN 690 B 5 1986, pp. 29-32, 116-117, 263-264, 919-921 (no month).
K. Kikuta et al.; "A1-Ge Reflow Sputtering for Submicron-Contact-Hole Filling"; VMIC Conference, Jun. 11-12, 1991, pp. 163-169.
K. Kikuta et al.; "0.25.mu.m Contact Hole Filling by A1-Ge Reflow Sputtering"; 1991 Symposium on VLSI Technology, Digest of Technical Papers, May 28-30, 1991 pp. 35-36.

Affiliated with

Also associated with

Rating

High aspect ratio low resistivity lines/vias by surface diffusio does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High aspect ratio low resistivity lines/vias by surface diffusio, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High aspect ratio low resistivity lines/vias by surface diffusio will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-860488