Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Patent
1997-08-21
1999-01-05
Niebling, John F.
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
438255, 438964, H01L 2170
Patent
active
058560076
ABSTRACT:
A semiconductor processing method of providing a polysilicon film having induced outer surface roughness includes, a) providing a substrate within a chemical vapor deposition reactor; b) chemical vapor depositing an in situ conductively doped amorphous silicon layer over the substrate within the reactor at a first temperature, the first temperature being below 600.degree. C., the doped amorphous silicon layer having an outer surface of a first degree of roughness; c) within the chemical vapor deposition reactor and after depositing the doped amorphous silicon layer, raising the substrate temperature at a selected rate to an annealing second temperature, the annealing second temperature being from 550.degree. C. to 950.degree. C.; and d) maintaining the substrate at the annealing second temperature for a period of time sufficient to convert the doped amorphous layer into a doped polysilicon layer having an outer surface of a second degree of roughness, the second degree of roughness being greater than the first degree of roughness, the substrate not being removed from the reactor nor exposed to oxidizing conditions between the time of deposition of the amorphous silicon layer and its conversion to polysilicon.
REFERENCES:
patent: 5037773 (1991-08-01), Lee et al.
patent: 5102832 (1992-04-01), Tuttle
patent: 5112773 (1992-05-01), Tuttle
patent: 5244842 (1993-09-01), Cathey et al.
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5302540 (1994-04-01), Ko et al.
patent: 5318920 (1994-06-01), Hayshide
patent: 5340765 (1994-08-01), Dennison et al.
patent: 5342800 (1994-08-01), Jun
patent: 5354705 (1994-10-01), Mathews et al.
patent: 5366917 (1994-11-01), Watanabe et al.
patent: 5385863 (1995-01-01), Tatsumi et al.
patent: 5418180 (1995-05-01), Brown
patent: 5583070 (1996-12-01), Liao et al.
patent: 5597754 (1997-01-01), Lou et al.
patent: 5656531 (1997-08-01), Thakur et al.
patent: 5759262 (1998-06-01), Weimer et al.
Figura Thomas A.
Sharan Sujit
Mulpuri S.
Niebling John F.
LandOfFree
Method and apparatus for forming features in holes, trenches and does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for forming features in holes, trenches and, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for forming features in holes, trenches and will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-860370