Divider circuit

Details Divider circuit Divider circuit

1987-11-19

1989-07-04

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Having phase shift

377 47, 377104, 377111, H03K 2102

Patent

active

048457272

ABSTRACT:
A pulse train divider circuit includes a first flip-flop (1) whose Q output is connected to the D input of a second flip-flop (2) whose Q output is connected to the D input of the first flip-flop (1). A pulse train to be divided is applied via an input (3) directly to the clock input C of the first flip-flop (1) and via a circuit (4) which delays the pulse train applied to the clock input C of the flip-flop (2) to provide a given phase relationship between the pulse trains at the two clock inputs. The circuit divides-by-two, and the resulting divided pulse trains available at the various outputs have phase relationships depending on the phase relationship of the applied pulse trains at the clock inputs.

REFERENCES:
patent: 3153200 (1964-10-01), Wahrman et al.
patent: 3668423 (1972-06-01), Couch
patent: 3851258 (1974-11-01), Freedman
patent: 4300039 (1981-11-01), Avins
patent: 4366394 (1982-12-01), Clendening et al.
patent: 4574206 (1986-03-01), Todokoro et al.
patent: 4651334 (1987-03-01), Hayashi
Digital Troubleshooting by Gasperini p9-3, "D Flip-Flop" pub. by Muvonics Co., Cal. copyright 1975.

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