Multiple pass error correction process and apparatus for product

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371 37, G06F 1100

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048457140

ABSTRACT:
An error correction system (20) comprises a multi-pass controller (32) which operates through a controller/decoder interface (34) to supervise the execution of decoding passes by a decoder (30). The multi-pass controller (32) employs a correction procedure comprising a plurality of hierarchial strategies S(1), S(2), . . . S(N) for transitioning the procedure through a plurality of predetermined states. Upon completion of a decoding pass, a pass evaluator (70) evaluates the results of the decoding pass and uses the evaluation for establishing values for further operation. Further passes are executed in accordance with further states determined by the multi-pass controller (32), the further states having particular parameters associated therewith including a strategy selection.

REFERENCES:
patent: 4456980 (1984-06-01), Yamada
patent: 4670881 (1987-06-01), Imoto
patent: 4719628 (1988-01-01), Ozaki
patent: 4742517 (1988-05-01), Takagi

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