Patent
1997-08-08
1999-08-03
Sheikh, Ayaz R.
395306, 395872, 395880, G06F 1314
Patent
active
059336153
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to the coupling of data word transfer devices in computer systems, in particular the coupling of different-speed bus systems.
Two bus systems operating at different data rates can be coupled via memory modules called FIFOs, for example the Type 74ALS2233 from Texas Instruments. These modules have a memory with two access paths via which, simultaneously, a transmitter can store data and a receiver can read data. Counters contained in the module are used to output the data in the sequence in which it is stored. In this case, the module provides signals which indicate that the input section is full and that the output section is empty. The former signal is used to stop the transmitter if the receiver has not been able to receive the data sufficiently quickly. The second signal causes the receiver to accept the data. If the transmitter is transmitting the data words in packets in which the data words follow one another more quickly than the receiver can process them, but there is a relatively long pause between data packets from the transmitter, then the receiver can process the data at a medium speed. If the receiver has a higher acceptance rate than the transmitter, a filling level signal for, for example, half-full, is frequently provided. Only when the buffer store is half-full is the receiver started for acceptance, and then accepts data until the buffer store has become empty. In this case, the transmitter and receiver frequently operate in the asynchronous mode, in which the transmitter transmits at times that are not predetermined and the receiver allows a variable length pause between two data words.
In computer systems and, in particular, in the case of access to bus systems, arrangements are used in which data packets comprising a predetermined number of data words are transmitted without interruption, also called the synchronous mode. The FIFO buffer stores mentioned above are also used if the clock rates of the transmitter and receiver differ.
A known application of FIFO memories in synchronous bus systems comprises the entire data packet initially being stored in the buffer store, with the transfer to the receiver being initiated at the end of the data packet, once all the data words are in the memory. However, the transmission rate of this arrangement is considerably less than that of the transmitter or receiver. Because of the synchronous operating mode, in contrast to the asynchronous operating mode, the transmission to the receiver (the data sink) cannot take place until it is certain that the data packet can be sent without interruption. This is undoubtedly the case once the data source has completed the transmission process. The loss of bandwidth in the case of this simple method thus corresponds to the duration of data transmission on the faster bus.
An improvement can be achieved if the outputting to the receiver has already started even though the transmitter has not yet transmitted all the data. Since the transmitter transmits continuously, it is possible to determine in advance, for a predetermined transmission and reception clock rate, the buffer store filling level beyond which the transmission to the receiver can be started. The calculation of the filling level in this case has to assume the worst-case boundary conditions, that is to say, if the transmitter is slow in comparison with the receiver, the slowest input clock rate and the fastest output clock rate. If the input clock rate is higher than the assumed slowest input clock rate, then the output to the receiver starts later than the optimum time. This results in lost waiting time or a delay for the transmitter between two data packets.
For example, if a central processor unit is being operated on a peripheral bus, the clock rate on the bus from the transmitter can be changed. The buffer store must then be designed for the slowest peripheral, as a result of which faster peripherals cannot achieve the maximum data packet repetition frequency and are thus not connected optimally.
REFERENCES:
patent: 4860193 (1989-08-01), Bentley et al.
patent: 5210829 (1993-05-01), Bitner
Etienne Ario
Sheikh Ayaz R.
Siemens Nixdorf Informationssysteme Aktiengesellschaft
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