Optical: systems and elements – Prism – With reflecting surface
Patent
1993-12-10
1999-08-03
Rinehart, Mark H.
Optical: systems and elements
Prism
With reflecting surface
39520068, 359117, G06F 1338, G06F 1517
Patent
active
059336080
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to memory devices incorporated in wafer scale integrated circuits.
2. Related Art
In integrated circuit fabrication, a single crystal is generally formed and then sliced into wafers. Each wafer is then processed using conventional fabrication techniques to form an array of identical integrated circuits, and the array is then cut into pieces on each of which is one of the integrated circuits.
Because of the variability of fabrication techniques, the yield of working integrated circuits rarely approaches 100%. After testing, circuits which do not work are not used.
Recently, interest has grown in wafer scale circuits; that is, integrated circuits which make up the whole or a substantial part of the area of a wafer. A very large number of circuit components can be manufactured on a wafer, with the connections between the components provided in the fabrication process so that the distance between adjacent components is small and communications between components on the wafer are fast. However, parts of the wafer will almost certainly be defective, and the defects will vary from wafer to wafer. It is therefore necessary for wafer scale circuits to be tolerant of such defects if they are to be usable. For this reason, to date, only very limited use has been made of wafer scale circuits.
One strategy for providing fault tolerant wafer scale circuits, as discussed in our earlier International application no. WO89/07298, is to provide that the circuit comprises an array of a large number of similar components interconnected by a communications network, and to carry out a test to determine which of the components and which parts of the network are not working. WO83/02019 proposes a wafer device comprising a plurality of cells (which can be memory cells) which are tested to establish their operating condition.
It has also been proposed to utilise wafer scale integrated circuits to provide an array of data processors on a large scale, to deal with parallel processing algorithms. Our above referenced application describes one approach, and another is described in "An Interconnection Scheme for a Tightly Coupled Massively Parallel Computer Network", J D Harris and A G T Connell, Proc IEEE International Conference on computer design: VLSI in computers, ICCD'85, PP612-616.
The prior art generally employs packet switching techniques in which messages are transmitted in separate packets.
SUMMARY OF THE INVENTION
We have realised, however, that a wafer scale integrated circuit can provide a high capacity, high speed communications switch. We have realised that the high bandwidth communications achievable internally within a wafer scale device can be used to provide a high capacity switch for interconnecting optical fibers, which have a similarly high bandwidth. Accordingly, in one aspect of the invention we provide a wafer scale circuit switching between a plurality of optical communications channels (preferably optical fibre channels).
A preferred embodiment of the invention comprises a plurality of such wafer scale integrated circuits, with optical communication channels disposed between the input ports of one circuit and the output ports of another. The input ports comprise opto-electrical transducers and the output ports comprise electro-optical transducers. Preferably, the optical communications channels comprise optical waveguides, for example optical fibres, disposed between the ports.
In another aspect, the invention provides a multi processor apparatus for data processing which comprises a plurality of processor units coupled to input and output ports of a wafer scale integrated circuit comprising a memory device, so that each can read data or write data through the memory device. Preferably, in this aspect, the memory device comprises a plurality of wafer scale integrated circuits as above.
Preferably, the invention performs circuit switching; in other words, opens and holds open a path through the wafer circuit through which messages
REFERENCES:
patent: 3486029 (1969-12-01), Barrett et al.
patent: 4063083 (1977-12-01), Cathey et al.
patent: 4290146 (1981-09-01), Adolfsson et al.
patent: 4393515 (1983-07-01), De Neumann
patent: 4733093 (1988-03-01), Graves et al.
patent: 4809358 (1989-02-01), Fernstrom
patent: 4826272 (1989-05-01), Pimpinella et al.
patent: 4850044 (1989-07-01), Block et al.
patent: 4937659 (1990-06-01), Chall, Jr.
patent: 5040168 (1991-08-01), Maue et al.
patent: 5237441 (1993-08-01), Nhu
patent: 5247593 (1993-09-01), Lin et al.
patent: 5268973 (1993-12-01), Jenevein
patent: 5287345 (1994-02-01), Osmon et al.
patent: 5335361 (1994-08-01), Ghaem
patent: 5392148 (1995-02-01), Takahashi et al.
patent: 5493437 (1996-02-01), Lebby et al.
Patent Abstract of Japan, vol. 8, No. 219, Oct. 5, 1984, JP,A,59 103166 (Fujitsu) Jun. 14, 1984.
Patent Abstract of Japan No. 62-179041, Aug. 6, 1987.
Patent Abstract of Japan No. 62-179042, Aug. 6, 1987.
Patent Abstract of Japan No. 62-179043, Aug. 6, 1987.
Patent Abstracts of Japan, vol. 12, No. 25 (P-659) (2872) Jan. 26, 1988.
FTCS 19 Digest of Papers; The 19th International Symposium et al, Jun. 20-23 1989, Chicago pp. 93-100 Kung & Song `Comprehensive Evaluation et al`.
International Journal of Electronics, vol. 69, No. 5, Nov. 1990, London, GB pp. 665-671, Choi `Design of Self-Testable Wafer-Scale Processor Arrays`.
IEEE Journal of Solid-State Circuits vol., 26, No. 5, May 1991, New York pp. 717-726, Change & Fuchs `Loop-Based Design and Reconfiguration et al`.
Computer Communication Review vol. 18, No. 4, Aug. 1988, New York, pp. 25-34 Karol `Optical Interconnection Using Shufflenet Multihop Networks in et al`.
"Universal Switching Network: Application to a WSI SIMD Array" Wafer Scale Intergtion, 199 Int'l Conf, Boubekeur et al.
"Channel Complexity analysis for reconfigurable VLSI/WSI Proc", Application Specific Array Processors, 1990 Int'l Conf, Rhee et al.
Rinehart Mark H.
The City University
LandOfFree
Multiway signal switching device including a WSIC and optical co does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiway signal switching device including a WSIC and optical co, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiway signal switching device including a WSIC and optical co will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-857867